1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, it relates to a method for forming a metal line of a semiconductor device which is suitable for reducing TAT (turn around time) at the time of forming of a gate array, and for simplifying processing with no additional mask.
2. Discussion of Related Art
Generally, the gate array serves to selectively connect a plurality of gates arranged in parallel through a metal line.
The characteristics of device depend on how the metal line is connected.
That is, the existing standard cells are to predetermine the device and metal line structure before manufacturing a chip, while the gate array is to predetermine the gate and device to be connected in parallel and then decide the metal line in accordance with the specification of products where a chip is to be mounted.
The following description relates to a conventional method for forming a metal line of a semiconductor device, referring to the appended drawings.
All processing steps after fabricating of a device are the stand-by state until customer's demands.
That is to say, after the fabrication of device is completed and before a contact hole is formed to connect the device with the metal line, processing is stopped to comply with the demands of the customers having different metal line layouts.
Therefore, all processings are finally stopped, after fabricating of device, followed by the formation of interlevel insulating layers.
FIGS. 1a to 1d are cross-sectional views, showing a method for forming a metal line of a semiconductor device according to a conventional first preferred embodiment.
As shown in FIG. 1a, a first metallic layer is formed on a wafer 11, before covered with photoresist (not shown).
The photoresist is patterned by exposure and developing, before the first metallic layer is selectively removed by using a mask, so that a plurality of first metal lines 13 are formed.
As depicted in FIG. 1b, a first interlevel insulating layer 15 is formed over the surface of the wafer 11 including the first metal lines 13.
When the above-mentioned processing is finished, all processings are stopped until the first interlevel insulating layer 15 is selectively removed in accordance with the metal line layout provided by customers.
That is, the first interlevel insulating layer 15 is selectively removed to expose the surface of a random first metal line 13 among the plural first metal lines 13.
The random first metal line indicates a metal line required for forming a line to satisfy customer's demands.
First tungsten 17 is deposited over the surface of the wafer 11 including the exposed first metal lines 13, and etched back away.
As shown in FIG. 1c, a second metallic layer is formed all over the surface of the wafer 11 including the first tungsten 17 and first interlevel insulating layer 15 and selectively removed to form second metal lines 19.
Here, one of the second metal lines 19 is electrically connected to the above random first metal line 13 by means of the first tungsten 17.
As illustrated in FIG. 1d, a second interlevel insulating layer 21 is formed over the surface of the wafer 11 including the second metal lines 19.
And then the second interlevel insulating layer 21 is selectively removed to expose the surface of a random second metal line 19 among the second metal lines 19.
The random second metal line 19 is also selected in accordance with the customer's demands.
Second tungsten 23 is deposited over the surface of the wafer 11 including the exposed second metal lines 19 and second interlevel insulating layer 21, and etched back away.
The repetition of such a processing serves to perform the multilayer metal line process.
FIG. 2 shows a method for forming a metal line of a semiconductor device according to a conventional second preferred embodiment, which is an FPGA (field programmable gate array) presented by Light speed in U.S.
As shown in FIG. 2, the method presented by Light speed is directly connecting two metals by using laser beam, in order to form a metal line.
That is to say, a via contact hole 35 is formed to electrically connect lower metal line 31 with upper metal line 33 that is formed by interlevel insulating layer (not shown) interposed therebetween.
Metal 37 connected to the via contact hole 35 is connected with the upper metal line 33, to form a metal line.
The region (dotted line) where the two metals 33 and 37 are connected, is irradiated by laser beams, to directly connect the two metals 33 and 37.
This intends to reduce TAT by using laser beams after metal patterning, in comparison with the conventional first preferred embodiment.
The conventional method for forming a metal line of a semiconductor device as constructed above has the following problems.
First, according to the conventional first preferred embodiment, all the processings after fabricating of device are stopped until customer's demands, so that it takes much time TAT to fabricate a chip after first processing.
Second, according to the conventional second preferred embodiment, two metals are directly connected with each other. Here, the contact between two metals is poor, thereby deteriorating the reliability of device.
Third, according to the conventional first preferred embodiment, process is performed in the range of 7.about.12V. Therefore, the line of device is less than 0.5 .mu.m, namely, 0.35 .mu.m, 0.25 .mu.m in width, resulting in the junction breakdown due to high voltage. And then FPGA chip cannot be used in the range below 0.5 .mu.m.